The present invention relates to packaging of electronic devices. More particularly, the present invention relates to methods of forming a protective material layer at the wafer level to protect at least portions of active surfaces and edges of chip scale packages including electronic devices.
Factors of cost and density are increasingly important in the electronics industry. Conventionally, high-density electronic devices in the form of semiconductor dice are packaged in transfer molded housings for protection from the environment and to provide electrical connections with the higher-level circuit structures into which they are incorporated. In an effort to reduce size and expense, semiconductor manufacturers have developed chip scale package (“CSP”) structures, which add minimal physical dimension to the completed devices and eliminate capital expense and processing steps associated with conventional packaging methods.
The formation of CSP structures may involve forming a dielectric layer adhered directly on one or more surfaces of a semiconductor die to seal and protect it from mechanical and environmental damage. In conventional CSP-forming processes, a passivation layer is typically formed on the active surface of a semiconductor die with apertures to expose the die bond pads, and an under-bump metallization (UBM) layer may be formed over the exposed bond pads to facilitate wetting of material of a conductive bump, such as a tin/lead solder, to be formed thereon to provide input/output, or “I/O,” connections for the CSP. The UBM layer may also, alternatively be located across the passivation layer remote from original bond pad locations at ends of conductive traces in the form of a so-called “redistribution layer” to relocate the external contact (bond pad) locations for connecting the semiconductor die to higher-level circuit structures. In such an instance, another dielectric layer is typically formed over the redistribution layer, apertures through the dielectric layer exposing I/O pad locations at the end of the conductive traces where the UBM layer may be formed. Discrete conductive elements in the form of bumps or balls may then be formed on or attached to the UBM layer-covered external contact locations to enable connection with higher-level circuit structures by flip-chip attachment. A mask layer may optionally be applied to surround the external contact locations prior to forming conductive bumps, which prevents the bump material from wicking onto adjacent die surfaces. Alternatively, a tape automated bonding (TAB) attachment approach may be employed. Finally, a layer of polymer or other dielectric protective material is conventionally coated onto one or more additional surfaces of the die to complete the CSP. The completed CSP is typically no more than 1.2 times larger than the die itself.
A further advantage of CSP structures is that they may be fashioned wholly or in part prior to the singulation of a wafer containing a plurality of semiconductor die locations. This approach, often being referred to as “wafer-level packaging,” provides simultaneous formation of a large number of electronic device packages. After the desired circuitry, bond pads, passivation layer, optional UBM and mask layers for the electronic devices have been fabricated on the active side of the wafer, conductive bumps are provided using conventional formation methods. One widely used method is evaporative deposition of metal onto a mask. The mask is formed on the wafer with apertures corresponding to the bond pad or other external contact locations and metal is deposited in the apertures. Once enough metal is deposited, the mask is removed and the metal is reflowed by heating to a molten state to form a discrete conductive element in a final bump or ball shape.
Another alternative for bumping a wafer is to employ stencil printing. Rather than evaporating metal through a mask, a solder paste is screened over a stencil and fills apertures therein corresponding to the bond pad or other external contact locations. The stencil is removed from the surface of the wafer, and the solder is reflowed for bonding to the UBM. Once the conductive bumps are in place, the entire active side of the wafer may or may not be coated with the aforementioned CSP protective layer. This is accomplished by molding, spin-coating or otherwise applying the protective layer to the surface of the wafer by methods known in the art. The wafer is subsequently singulated to excise the individual semiconductor dice, and further protective layers may be added to coat any remaining exposed die surfaces.
A further alternative for wafer bumping is to place preformed metal balls, such as solder balls, on the wafer at selected locations. The wafer is then heated to at least partially melt the solder balls and metallurgically bond them to the UBMs or other contact structures on the wafer. As before, once the conductive bumps are in place, the entire active side of the wafer is coated with the aforementioned CSP protective layer. This is accomplished by molding, spin-coating or otherwise applying the protective layer to the surface of the wafer by methods known in the art. The wafer is subsequently singulated to excise the individual semiconductor dice, and further protective layers may be added to coat any remaining exposed die surfaces.
One disadvantage in conventional wafer-level packaging has been encountered due to the formation of the conductive bumps before applying the layer of dielectric protective material to the active side of the wafer. The layer often completely covers the conductive bumps or, if not, at least contaminates portions of the surfaces of the conductive bumps. Therefore, the dielectric protective material must be etched back, ground down or otherwise partially removed to expose the conductive bumps for electrical contact. Furthermore, surface tension between the dielectric protective material and the conductive bumps can cause irregularities during coating and thereby reduce the uniformity of the protective layer.
Another disadvantage in conventional wafer-level packaging has been encountered in connection with testing CSPs. A singulated die is typically placed in a test socket for testing. Contact between the CSP and the test socket, particularly at edges and corners of the active surface of the CSP, can cause damage to the integrated circuit of the device. Such damage is particularly likely to occur when residual particles remain in the test socket from prior use, providing point loading of the protective layer and the underlying active surface. Damage can also, and frequently does, occur in the ordinary course of handling CSPs.
Yet another disadvantage in known wafer-level packaging is warpage resulting from the formation of protective layers over an entire surface of a CSP, which results in lower yields of CSPs.
In view of the foregoing, there is a clear need for improved methods for wafer-level packaging that address the existing problems associated with forming protective layers in CSPs.